This International Standard describes the methodology applicable for environmental acceptance testing of tin-based surface finishes and mitigation practices for tin whiskers on semiconductor devices. This methodology may not be sufficient for applications with special requirements, (i.e. military, aerospace, etc.). Additional requirements may be specified in the appropriate requirements (procurement) documentation. This International Standard does not apply to semiconductor devices with bottom-only terminations where the full plated surface is wetted during assembly (for example: quad-flat no-leads and ball grid array components, flip chip bump terminations). Adherence to this standard includes meeting the reporting requirements described in Clause 6.